PCI - AER Adapter board

Draft

 

Vittorio Dante

 

Overview

Figure 1 illustrates the main components of the system under construction.

The system includes the main interface board (IB in what follows), connected via a cable to a small board which is directly connected to the AER bus.

The IB has three main components:

 

The MAPPER: essentially implements the connectivity pattern between up to four sender chips, and up to four receiver chips.

 

The MONITOR: allows to tap the transactions on the AER bus, to attach time information to them and to forward the joint information to a PC via PCI. Its available modes of operation allow acquiring every event from the AER bus or selecting events associated to a chosen subpopulation of neurons on the chips.

 

The SEQUENCER can be connected directly to the AER bus to emulate a neural chip, i.e. allowing the communication of a pre-determined flux of spikes from a simulation to subpopulations of neurons on the chips, to code the structure of ‘external stimuli’.

 

 

 

 

 

 

 

Figure 2 describes in more details the structure of the IB.

The MONITOR attaches a 32 bit time label to an AER event, and puts into the FIFO three 18 bit words for each event, according to the scheme of Table 1.

The SEQUENCER can generate events on the AER bus, emulating a further, virtual neural chip and/or a flux of external spikes to the neural chips. It includes a FIFO, the actual sequencer which scans the FIFO and executes the commands defined in Table 2 generating the appropriate AER events. The SEQUENCER has two modes of operation, depending on the setting of a flag, actually generating a AER event or bypassing the AER IN bus, inputting directly the event to the MAPPER

via the ARBITER (see below).

The MAPPER implements the connectivity structure of the multi-chip neural network (see Figure 3). The 16 bit AER label of an incoming event on the AER IN bus, is used as an index in a 64 Kwords lookup table. According to the setting of the highest two bits, the MAPPER can either use the remaining 22 bits as a pointer to the first word of a memory segment which implements the axon of the emitting neuron identified by the AER label. Or, the MAPPER can directly put an AER event on the AER OUT bus, using the AER label as the identifier of the target neuron. See Table 3 for the use of the highest bits of the words in the lookup table by the MAPPER.

 

 

Bit17,16

Bit 15..0

AER Adddress

00

AER Label
TIME HI

01

Highest Word of TIME
TIME LO

10

Lowest Word of TIME
Command

11

Command / Error Code

 

Comando

Bit17,16

Bit 15..0

End of sequence

00

 
AER transaction

01

AER Address
Delay

10

Delay in CLOCK AER
Wait TIME

11

Waits TIME before resuming execution

 

The System Counter (TIME) is a 32 bits counter, synchronous with AER clock. The latter has four programmable values (1,10,50,100 ms)

Pointer Table Bit 23,22 Bit 22..0
Puntatore NULL

00

000000H
Pnt. Inizio Table

01

Puntatore inizio all’Address Table 22 Bit
Pnt. Fine Table

10

Puntatore fine all’Address Table 22 Bit
Indir. Diretto

11

Address AER Bit 16..0

 

 

Figure 4 illustrates the structure of the cable adapter.

 

 

 

External board Layout

 

 

Board layout: